UniPHY Data Brief - Universal Physical Baseband Processor

UniPHY is the first ultra-high performance, fully synthesizable DSP core optimized for physical layer signal processing. UniPHY offers a flexible general-purpose solution to enable multi-standard PHY protocols.

With the ability to execute 12 parallel SIMD operations per clock cycle, UniPHY delivers the needed performance for DSP intensive applications such as:

Broadband Networking

Wireless LAN (802.11a, 802.11b, 802.11g, HiLAN2)

HomeRF

Fixed Wireless (MMDS, LMDS)

Broadband Modem

xDSL

Cable Modem


		Multi-standard PHY solution
		Support for evolving PHY layer standards
		ASIC level performance within a flexible platform
		Product differentiation through configurable datapaths and instructions


		Expansion instructions enable simultaneous untilization of all 12 SIMD execution units
		Datapath registers to boost data bandwidth
		SoftDatapaths™ for configurable/software programmable high-data throughout data paths


	Click here to see 3DSP's UniPHY presentation Data Brief


	2 way super-scalar issue
	SIMD instructions operate on 8/16/32 bit data
	SP-X™ instruction set compatible
	Automatic data and pipeline hazard detection during super-scalar execution
	4 multiplier units (2 32x32, 4 16x32, 8 16x16, or 16 8x16 multiplies), 4 48-bit accumulators
	8 arithmetic units containing application tailored combination of adders, shifters, logic units, and Viterbi accelerators
	32x32-bit general purpose register file (supports 4 register reads and 4 writes per cycle)
	Memory to register file architecture
	Hardware optimizations for key algorithms (e.g., Viterbi, FFT, FIR)
	All instructions can be predicated
	Zero overhead looping

	Single clock edge, flip-flop based design
	VHDL/Verilog based RTL code
	Ease-of-synthesis coding style

	Fully gated functional units
	Programmable clock frequency
	Sleep mode

	32-bit orthogonal instruction set
	Efficient code to processing ratio via combination of SP-X™ and expansion instructions
	Complex multiply, add-sub instruction
	8-bit, 16-bit SIMD add, sub, mult, MAC, shift, saturation instructions
	Barrel shift, signed, unsigned instructions
	Bit manipulation instructions: set, clear, extract, insert, pack
	Register indirect addressing mode

	Efficient code density to processing ratio
	Balanced code complexity to performance tradeoff



	Program memory configurable as either 2-way set-associative cache or direct-mapped SCRAM (memory) with prefetch and cache-line locking
	A, B data memory supports up to 4 32-bit memory load/store per cycle
	Data memory Byte, Half-word, Word addressable
	DSP address generation unit supports 8 circular buffers, with transpose mode for 2-D data manipulation, bit-reverse. Capable of generating 4 addresses per cycle
	4 page registers
Hardware Stack supports push and pop; highly efficient context switching
Full debug support with real-time tracing
Full scan design

	C compiler and cycle accurate C simulator
	C/Assembly debugger and code profiler
	Software Studio™ (Windows based integrated development environment)