The SP-5 is a fully synthesizable DSP Core based on the high performance, low power, SuperSIMD™ (Super-scalar, Single Instruction Multiple Data) proprietary architecture. The SP-5 provides an optimized balance between performance, power, cost and ease of programming.

The SP-5, available with 24x16 or 32x32-bit multipliers configurations, delivers the needed performance for DSP intensive applications such as:

High Density VoP (Voice-over-Packet) G.7XX Vocoders G.168 - 2000 Echo Canceller DTMF VAD/CNG Digital Wireless 3G Radio Modem CDMA, TDMA, GSM Vocoders

Video & Imaging MPEG-4 H 263 Multi-Frame Camera Audio AAC AC-3 MPEG-1/2 MP3 Broadband Modem xDSL Cable Modem

Reduced time to market
Reduced development risk
Improved system performance
Simplified SoC integration

Data Brief White Paper Application Notes Request Manuals

Superscalar issue, executes two
instructions per cycle
Multiple data instructions
Hardware automatically detects and
handles all data and pipeline hazards
4 48-bit Accumulators
Maximum size of 24x16-bit or
32x32-bit Multipliers
32x32-bit General Purpose Register File
All instructions conditional
resolution
Static branch prediction, dynamic
branch resolution
Minimal branch overhead


Single clock edge, flip-flop based design
VHDL/Verilog based RTL code
Ease-of-synthesis coding style



Fully gated functional units
Programmable clock frequency
Sleep mode
Minimal clock power consumption



32-bit orthogonal instruction set
Bit manipulation instructions: Set, Clear,
Extract, Insert, Pack
24x16-bit or 32x32-bit Multiply, MAC,
Multiply-Subtract instruction
8-bit, 16-bit SIMD Add, Sub, Mult, MAC,
Shift, Saturation instructions
Barrel Shift, Signed, Unsigned instructions
Conditional Branch
Register indirect addressing mode

31 Prioritized Interrupts, Supports
Nested Interrupts, 2 Cycle Typical
(7 Maximum) Interrupt Latency

Hardware Stack, Supports Push and
Pop. Highly Efficient Context
Switching

Since the SP-5 is a fully synthesizable core, it can be targeted for almost any process technology. Featuring a QUAD MAC architecture (4 MACs per cycle on 16-bit data), the following typical performance and core size is achievable:

Process	0.25 µm	0.18 µm	0.13 µm
Clock Speed	160 MHz	220 MHz	320 MHz
MAC/Sec @16-bit	640M	880M	1280M
GOP/Sec @8-bit	3.8	5.3	7.7
Die Area	3.6 mm2	2.5 mm2	1.6 mm2

Typical application power consumption

Voltage	2.5 V	1.8 V	1.0 V
Process	0.25 µm	0.18 µm	0.13 µm
Power	150 mW	77 mW	25 mW

Program Memory can be incrementally
configured as SRAM or Set Associative Cache
A, B Data Memory Supports up to 2 Memory
Load/Store per Cycle
Data Memory Byte, Half-word, Word addressable
DSP Address Generation Unit Supports 8 Circular
Buffers, with Transpose Mode for 2-D Data
Manipulation, Bit-Reverse, capable of generating
2 Addresses per Cycle
4 Page Registers

JTAG Debug Port, DSP Break on Program
Counter, Status Register, Memory
Address

Full Scan Design