3DSP

The 3DSP HiFI configuration tools enable designers to quickly find an optimum DSP system architecture for their application. In a series of quick iterations, the user is able to describe different system architectures and test the performance of those architectures. The system architecture can be optimized by:

Customizing the DSP core
Configuring the memory sub-system
Matching the I/O system capacity to needs
Adding proven peripheral devices

The included Software Studio™ development tools are automatically configured to match the selected system configuration. Users can immediately measure the performance of the architecture by running application code on a cycle accurate model.

The easy-to-use graphical user interface (GUI) displays the current configuration information on an automatically updated block diagram. With the appropriate licenses, HiFI outputs fully synthesizable RTL code that is ready to be integrated in the user's IC or FPGA.

Customized DSP core creation
Optimized I/O configuration
Reuse of proven peripherals
Reduced development cost

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	Data Brief Data Sheet Application Notes Request Manuals

	Easy to use point and click tool
	Power, speed, cost trade-off analysis

	Application-specific instructions
	General registers structure
	Execution unit structure
	Address generation unit structure
	Immediate constants
	Number of stack pointers
	Maximum multiplier size
	Number of shift units
	Application-specific logic unit

Program memory

2-64K words

Data memory

	Individually configure A and B memories
	1-16K words each

Interrupt units 0 or 1

Timers 0, 1, or 2

GPIO port 0-32 bits

DSP memory port

Single or dual port

Clock speed for power estimation

	Memory management unit and BIST
	External memory interface
	JTAG test and debug port
	UART
	CCD imager interface
	Clock management unit
	High speed ARM/AHB bridge

System Bus Controller

Clock speed for power estimation

Number of channels 1-15

Number of ports 1-16

Number of requestors (processors)
1-8

Configure each port individually

	Memory, I/O or processor interface
	Synchronous or asynchronous
	Read buffer size
	Write buffer size
	FIFO mode on or off
	Port type: uni-directional, bi-directional, or SDRAM three buffer
	Port address width
	Port clock speed
	Interrupt level assigned to each port

	USB interface
	PCI interface
	I2C interface
	I2S interface
	H.100 interface
	T1/E1 interface
	Reset generator
	Video output interface